EXPERIMENT 14

Introduction to Digital Logic

In this experiment we begin addressing the concepts of digital electronics, which is discussed rather well in Chapter 7 of Gingrich. Before looking at some of the basic building blocks of digital circuitry, we will first consider some of the advantages of this branch of electronics.

Part A Comparators and Schmitt Triggers

In the circuit above, you will see that we have no feedback for the op amp. Thus, any positive voltage across the inputs will cause the output to go as positive as it can and any negative voltage across the inputs will cause the output to go as negative as it can. The range of outputs is limited by V_CC. Thus, the output should go to about +V_CC whenever the input is positive and to -V_CC whenever the input is negative. This is an example of a comparator. The voltage at the + terminal is compared to the voltage at the - terminal. When V⁺ > V^- then V_out = V_CC and when V⁺ < V^- then V_out = -V_CC. Simulate (transient analysis with a time step of 1us from zero to 3ms) the circuit above to demonstrate that this indeed does happen. Print one plot of your output per group.

If all we could ever do was to check the sign of a voltage, this kind of logical operation would be of limited usefulness. Also, you should be able to see that a simple comparator circuit is very noise sensitive. If the input signal is about zero volts but has a lot of noise on it, the output will keep switching between +V_CC and -V_CC following the noise. It would be more useful to have a comparator-type circuit that switches output state when the input exceeds some finite threshold rather than just zero. A Schmitt Trigger configuration makes this possible. In the circuit below, the output will switch when the input exceeds BV_CC or is less than -BV_CC where B = R3/(R3+R4). Show that this is the case. Hint: the voltage V⁺ at the positive input is related to the output voltage V_out by the voltage divider action of resistors R3 and R4.

Now simulate this circuit (same transient analysis as above) and show that it indeed changes its output state as it should. Print one plot per group. Be sure that your input level is large enough to make the circuit switch states, but not too large so that it is difficult to observe where the switching occurs.

A Schmitt Trigger can be further generalized as is shown below. Simulate this circuit (same transient analysis as above), print one plot per group and discuss what it does. Be sure that you use a large enough amplitude for V3 so that the output switches between saturated states, but again not so large that it is difficult to see where the switching occurs.

Thus far, we have considered a fairly general model of a Schmitt Trigger. The particular device we will use in our experiments is an SN7414 or equivalent. A model for the 7414 is included with the Microsim PSpice program. Simulate (same transient analysis) the circuit below in which we have included two voltage sources to crudely show what happens when noise is added to a signal. For V1, use an offset of 1.5V, an amplitude of 1.5V and a frequency of 1k. For V2, use no offset, an amplitude of 0.2V and a frequency of 100k. Again produce only one plot per group. You might want to expand the time scale around one of the transition points to verify that the output changes state only once. Check to be sure that the device performs as it should by looking up the characteristics of the SN7414 on the Texas Instruments website. There is a link to the page for this device in the Helpful Info section of the course webpage. You should find links to information on all the logic devices we will be using. The pages that will come up contain general information. The actual device datasheet is a pdf file.

What are the typical switching thresholds for this device and does the PSpice work as expected? (Look at the recommended operating conditions in the datatsheet.) Also, you will notice in the diagram above that there are no power connections to this device. Why is it not necessary to include them for the simulation?

In preparation for the next part of this experiment, please read Chapter 7 of Gingrich. You should skim through the entire chapter and read carefully through section 7.4.4.

Part B Basic Logic Gates

Binary logic has two values, called TRUE and FALSE or LOGIC 1 and LOGIC 0 or ON and OFF or HIGH and LOW. The corresponding binary number can have two possible values, 1 and 0. In TTL digital electronic circuits, the corresponding definition in terms of voltages is about 5 volts for LOGIC 1 and about 0 volts for LOGIC 0. About 5 volts usually means any voltage between 3 and 5 volts while about 0 volts means any voltage in the range 0 to 2 volts. The two output levels of the Schmitt Trigger you just simulated are examples of practical values for LOGIC 1 and LOGIC 0. (Aside: the output levels from TTL devices will be in the ranges indicated. These are the only output levels one should see with logical devices. This is one characteristic that differentiates them from analog devices. They also switch very fast from one state to the other. Switching speeds are usually much faster than for analog devices, especially cheap devices like the 741 op amp.)

We will now consider three basic logical elements: a two input NOR gate, a three input NAND gate and an INVERTER. A circuit containing all three devices is shown below.

Links to the specifications for each of these devices can be found in the Helpful Info section of the course website. We will both simulate these devices and see how they work on a protoboard. First the simulation. We will use three digital clocks, which output a sequence of pulses at the two TTL levels. To differentiate between the three clocks, we will set them up to work with different pulse lengths. Use the default settings for the first clock (no delay, on time = 0.5us, off time = 0.5us). For the second clock double the on and off times to 1us. For the third clock, double them again to 2us. Simulate 4us of signals with a step size of 0.01us. For PROBE, display the three clock signals each time, but display only the output voltage level for one gate at a time. Otherwise, the signals are difficult to tell apart. Produce a hardcopy of the plot for only the output of the three input NAND gate. These plots are examples of timing diagrams, which are discussed in section 7.4.4 of Gingrich. For each gate, generate the truth table for the device, based on the outputs and inputs you observe in the timing diagrams. Do your results agree with the truth tables in Gingrich on page 136 and/or in the datasheets for the devices?

Wire the circuits on a protoboard as shown on the figure above. You will have to check the datasheets (using the links in Helpful Info) to determine the pinouts for these chips. We used the digital clocks for the simulation, since they make the output plots more useful. For the experiment, we will use the function generator and DC sources. Set up the function generator as follows. (This procedure should always be used when the function generator is the source.) Connect the function generator to channel 1of the scope so you can see what your input is actually like. Adjust it so that it is producing 1kHz square waves with an amplitude of 5volts and a duty cycle of 20%. By having the function generator ON (5volts) for 20% of the time and OFF (0volts) for 80% of the time, you will be better able to identify when the inputs are ON and OFF. Remember to rely on the scope to set up the function generator, not the panel readings. Now use the function generator as the top source (which is connected to all three devices). The second and third source voltages will be set by connecting them to either ground (0volts) for logic ZERO or to V_CC = +5volts for logic ONE. Test each device in turn by connecting its output to channel 2 of the scope. Generate the truth table for each device. The data you collect can just be put in the truth table rather than saving lots of scope traces. However, for the record, you should print out one of the scope traces and indicate on it how you determined the information in your truth table.

Part C Application of a Schmitt Trigger

As we saw in Part A, the purpose of the SCHMITT TRIGGER is to convert an analog voltage into a binary digital voltage. When the input voltage of the SN7414 exceeds a threshold of 1.7volts, the device output switches to LOGIC 0; the input voltage must drop below 0.9volt for the output to switch back to LOGIC 1. (This device exhibits hysteresis.) The difference in thresholds is very important in preventing false triggering on noise. The device is also inverting, but the SCHMITT TRIGGER does not behave in the same manner as the INVERTER.

Set up the circuit shown on the protoboard. Remember that the 50ohm resistor is the internal resistance of the function generator. Set the function generator for sine wave output with a frequency of 1kHz and an amplitude of 5volts. Be sure you have both the input and output connected to the scope. Print out the scope trace. On the plot, indicate the features of the signals that demonstrate hysteresis.

Modify the SCHMITT TRIGGER circuit as shown below. Diode D1 is a photodiode, diodes D2 and D3 are LEDs. The photodiode circuit is an optical detector that we will use as a scanner. Use the scope to observe the voltages across the two 1k output resistors. Run a flashlight over the photodiode. What do you observe? What is different about the SCHMITT TRIGGER output and the INVERTER output?

Part D Flip Flops

It is possible using basic logic gates to build a circuit that remembers its present condition. It is also possible to build counting circuits. The basic counting unit is the flip flop. Please read through sections 7.9 and 7.10 of Gingrich with particular emphasis on the JK FLIP FLOP, which we will be using here. You should also look over the datasheets for JK FLIP FLOPS listed in Helpful Info.

JK FLIP FLOPS, like other FLIP FLOPS have four inputs, two outputs and the usual two power connections (V_CC and ground). The outputs are labeled Q and Q (also Qbar and NQ), which are complements of one another. Thus, when Q is LOW, Q is HIGH, etc. The input CLR (or CLRbar), when LOW will reset the outputs to a known state. Since this device has memory, it is very important to be able to first initialize it to a known state. Otherwise, we will not know what it is doing. The CLK is the digital clock. Each time the clock pulse goes HIGH (5V) the values at the inputs J and K are read. These are the logical inputs to the device. On the falling edge of the clock pulse, the FLIP FLOP will change state based on the values of these inputs and its present output state. Please check the datasheet for the SN74107 FLIP FLOP to see what the truth table for this device should be.

We will use PSpice to produce the timing diagram for the SN74107 FLIP FLOP. Use the digital clock for all of the input signals. Set up the clocks as follows: Clock 1 ONTIME = OFFTIME = 1us, Clock 2 ONTIME = OFFTIME = 0.5us, Clock 3 ONTIME = OFFTIME = 2us, Clock 4 ONTIME = 12us OFFTIME = 4us. Run the transient simulation for 16us with a step of 0.01us. Place voltage markers near the pins on the FLIP FLOP. Then the output seen with PROBE will be labeled with the pin names so you can easily see the function of the signal. Print out this plot and use the information it contains to confirm that the truth table in the datasheet is correct.

Set up the 74107 JK FLIP FLOP on the protoboard. Use the function generator for the clock. Set it for a square wave frequency of 1kHz. Use the offset feature to shift the square wave up such that it cycles between 0V and 5V. Be sure that you use the scope to check the operation of the function generator. Use the ground (0V) and +5V connections on your protoboard to supply the required logic levels for the J, K, and CLR. First set the CLR to zero to be sure that the FLIP FLOP begins in a known state. Then set it to +5V to check out the four possible combinations of J and K. Observe the output Q on channel 2 of your scope and the clock on channel 1. Construct the experimental truth table for this device.

Part E A Counter

JK FLIP FLOPS can be connected in a counter configuration. It is not necessary for us to configure several FLIP FLOPS into a counter, since this is already done in many kinds of chips. The SN74393, for example, has two sets of four JK FLIP FLOPS connected as binary counters. If you have forgotten how binary counting works, look at Table 7.1 in Gingrich to see how to count from 1 to 16. There are two counters in this chip (that is why it is called a dual counter). To simulate it using PSpice, it is easiest to use two separate counters as shown below, even thought they are actually in the same chip. For this simulation, Clock 1 is a normal clock with ONTIME = OFFTIME = 0.5us. Clock 2 is set up so that it first clears the counters and then lets them count. To do this, the ONTIME is set very long and the OFFTIME is set very short. The start value and operating values are also reversed from the usual specification. You do not need to be too concerned about the details of this, since you will not be doing the actual simulation. However, you might be asked how to do this at some later date. By connecting the two counters together as shown, the sequence of numbers 2QD, 2QC, 2QB, 2QA, 1QD, 1QC, 1QB, 1QA are the binary number. Since the counter is set up to count clock pulses, it will count up from 0 to the number of pulses sequentially. Shown on the next page is the PROBE output for this circuit. Using this output, verify that the counters are actually counting. What is the highest number it counts to in the time shown? Express this number both as a binary number and a decimal number. How many pulses will the clock have to cycle through before the counter hits its maximum value?

For the hardware implementation of this counter, you will not be given a circuit diagram, just general instructions. Use the function generator in place of the first digital clock. Set its frequency to something very slow like 1Hz. You will need to look at the datasheet to see the pinouts for this device. Remember that both counters are in the same chip. First connect the CLR to +5V to reset the counters. Connecting it to zero after that will start the count. (Actually it works just as well to leave CLR connected to ground and cycle the DC power supply off and on to reset the counter.) To observe the counting, connect an LED to each of the 8 outputs. Place them in order on your board so that you can read the binary number. Be sure that you put a current limiting resistor in series with the LEDs. You can use the resistor to connect from the chip to the LED array. You can experiment with the resistor value. Smaller resistors will make the LEDs brighter, but the chip might get too hot. We know that about 1k ohm is safe from past experience, so you might want to start there or around 500 ohms. Sketch the circuit diagram that works well for you. Make sure that you show a TA that your circuit is counting correctly.